Implementation of Modified FEC Codec and High-Speed Synchronizer in 10G-EPON
نویسندگان
چکیده
This article puts forward parallel forward error correction(FEC) codec for 10 Gb/s Ethernet passive optical network (10G-EPON) , which adopts 8-parallel algorithm based on improved state space transformation (SST) method for Reed-Solomon (RS) encoder and 9-parallel algorithm based on enhanced degree computationless modified Euclid’s (EDCME) algorithm to solve the key equation for RS decoder. The designed 10 Gb/s codec and high-speed synchronizer are implemented with Verilog HDL on Xilinx FPGA ML523. The implementation results show that, with the high-speed synchronizer, the RS (255, 223) encoder and decoder are able to operate at 15.232 Gb/s and 13.2 Gb/s respectively with shorter time latency than those of the reported designs. Copyright © 2014 IFSA Publishing, S. L.
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